- Amita Nandal
- Ashwani K. Rana
- S. Nirmalraj
- E. Chitra
- Antim Bala Sharma
- Ajay Sharma
- Fanibhushan Sharma
- Nirmala Sharma
- V. Sarada
- P. T. Thasneem Salim
- Akhilesh Murikipudi
- V. Prakash
- Jonnalagadda Raghavendra
- Madhu Lodhi
- Visalakshikaleeswaran
- R. Kirthika
- N. P. Prabu
- M. Rakesh Mohan
- S. G. Wasim Ahamed
- Vigil Dev Asir
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Vigneswaran, T.
- Booth Multiplier Using Reversible Logic with Low Power and Reduced Logical Complexity
Authors
1 Department of ECE, NIT Hamirpur-177005, Himachal Pradesh, IN
2 School of Electronics Engineering, VIT University, Chennai-600127, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 7, No 4 (2014), Pagination: 525-529Abstract
The proposed testable reversible architecture scheme yields significantly reduced complexity, low power and high speed features. It is a key issue in the interface of computation and physics, and of growing importance as miniaturization progresses towards its physical limits. With the advent of nanotechnology the fault detection and testability is of high interest for accuracy. This research work describes the reversible testable design of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm can be used to accelerate the multiplication speed with reduced power consumption. The resultant multiplier circuit shows better performance than others and can be used in the systems requiring very high performance. The proposed booth multiplier design shows 12% reduced logical complexity, 10% reduced power consumption and efficient device utilization achieved in comparison to existing reversible logic.Keywords
Barrel Shifter, Booth Encoding, Booth Multiplier, Logical Complexity, Partial Products, Reversible Gate And Testability- A Novel Cascaded Image Transform by Varying Energy Density to Convert an Image in to Sparse
Authors
1 Department of E.E.E, Sathyabama University, IN
2 Department of E.C.E, VIT University, Chennai, IN
Source
Indian Journal of Science and Technology, Vol 8, No 8 (2015), Pagination: 766-770Abstract
Background: All natural signals are subjected to sparsity when they are properly represented by a basis function. Sparsity helps us to sample the signals less than Nyquist rate which clearly explained by the recent theory known as compressive sensing. Methods: This paper explains that DFT does a good job in converting the given image into sparse when the energy density of the image is varied and also a cascaded transform DFT and DWT is proposed. Qualitative measures for the cascaded transform were observed to be good. Result: It helps us to convert a given image signal into sparse without loss in information content present in that image. Application: While converting an analog signal into digital, sparsity will help to compress a given analog signal before conversion. So the number of samples obtained by sampling the compressed signal becomes less.Keywords
Compressive Sensing, Energy Density, Image Transforms Information Preservation Capability, Sparsity.- An Efficient Barrel Shifter Design Using Testable Reversible Logic
Authors
1 Electronics and Communication Department, SRM University, Chennai, IN
Source
Programmable Device Circuits and Systems, Vol 3, No 8 (2011), Pagination: 396-401Abstract
Data shifting is required in many key computer operations from address decoding to computer arithmetic. With the advent of quantum computer and reversible logic, the design and implementation of all devices in this logic has received more attention. The various operations like arithmetic and logical operations, address decoding and indexing etc., require data shifting and rotating. For high speed applications the barrel shifters become more popular which can shift and rotate multiple bits in a single cycle. In this research work, a reversible barrel shifter structure, computation delay and power consumption is presented which outperforms the conventional design. The experimental result shows that the proposed reversible barrel shifter has 5% higher speed and 10% power efficient as a single unit when compared to the conventional barrel shifter design.
Keywords
Barrel Shifter, Multiplexer, New Gate, New Testable Gate, Reversible Logic and Testability.- An Efficient Canonical Signed Digit Multiplier Design for Image Processing Applications
Authors
1 Electronics and Communication Department, SRM University, Chennai, IN
Source
Digital Image Processing, Vol 3, No 11 (2011), Pagination: 667-672Abstract
The main objective of today’s circuit design is to increase the performance without the proportional increase in power consumption. In this regard, reversible logic has become a promising technology in the field of low power computing, image processing applications and designing in implementation of Digital Signal Processing (DSP) algorithms in hardware, such as Field Programmable Gated Arrays (FPGAs) that requires a large number of multiplications. The arithmetic operations involved in signal processing systems increases computation complexity which in turn is related to system performance and hardware requirement. There are various methods which help to reduce the computation complexity significantly. In this research work, a reversible Canonical Signed Digit (CSD) multiplier structure is introduced. The various operations like arithmetic and logical operations, address decoding and indexing etc., require data shifting and rotating. For high speed applications the barrel shifters become more popular which can shift and rotatemultiple bits in a single cycle. For this reason, this research work presents an efficient design of a reversible CSD multiplier, which in turn uses the barrel shifter to perform the shifting operation. The main focus is on designing an efficient multiplier and then evaluates several significant parameters for this reversible circuit design. The experimental results shows that the proposed reversible CSD multiplier resulted better in terms of 10% reduced power consumption and 11% increased speed to those generated from the conventional CSD multiplier.Keywords
Barrel Shifter, Canonical Signed Digit, Color Transform, Feynman Gate, FIR Filter, Image Processing, New Gate, New Testable Gate, Reversible Logic and Testability.- An Efficient High Speed and Low Area Digital FIR Filter Design Based on Sectioning of Look up Table in Distributed Arithmetic Algorithm
Authors
1 Electronics and Communication Department, SRM University, Chennai, IN
Source
Digital Signal Processing, Vol 3, No 7 (2011), Pagination: 318-323Abstract
This research work presents an efficient implementation of Finite Impulse Response Filter (FIR) using Distributed Arithmetic (DA) architecture. Here, the multipliers in FIR filter are replaced with multiplier less DA based technique. The DA based technique consists of Look Up Table (LUT), shift registers and scaling accumulator. Analysis on the performance of various orders of the digital FIR filter with various methods of sections on different address length of partial tables are done using Xilinx 12.3 synthesis tool. The proposed architecture provides an efficient Very Large Scale Integration (VLSI) implementation which involves significantly less latency and less area-delay complexity when compared with existing structures of the digital FIR Filter. In this method, the multiplier less FIR filter is implemented using Distributed Arithmetic which consists of Look Up Table and then its partitioning is involved. This technique reduces the delay by 15%, area by 34% and LUT by 75%.Keywords
Distributed Arithmetic (DA), Finite Impulse Response (FIR), Field Programmable Gate Array (FPGA), Look up Table (LUT).- Design of High Performance Digital Fir Filter Using Distributed Arithmetic Algorithm with Residue Number System
Authors
1 Gurukul Institute of Engineering and Technology, Kota, IN
2 Department of Electronics and Communication Engineering, S.R.M. University Kattankuluthar, IN
3 Maharishi Arvind International Institute of Technology, Kota
4 St. Margaret Engineering College, Neemrana, IN
5 Rajasthan Technical University, Kota, IN
Source
Research Journal of Engineering and Technology, Vol 2, No 1 (2011), Pagination: 21-25Abstract
The use of the proposed method in residue to binary conversion in Residue Number System (RNS) and Distributed Arithmetic Algorithm (DAA) in modern telecommunication and multimedia applications is becoming more and more important because it allows interesting advantages in terms of area, power consumption and speed.. This paper presents new method for conversion procedure (residue to binary) based on a {2n -1,2n , 2n+1, 2n + 1+1, 2n - 1 -1} moduli set. Based on the proposed method for conversion in RNS and DAA algorithm, an architecture which efficiently implements the digital fir filter is synthesized using Xilinx Virtex2. Proposed method simplify the computing procedure by maximizing the utilization of the modulo-mi adders and multipliers present in the RNS functional units. For an n-digit RNS number X = (x1, x2, x3, …., xn) the proposed method takes at most n iterations. Each iteration requires one parallel subtractions and 2 multiplications except the first one.Keywords
Residue Arithmetic, Distributed Arithmetic, Fir Filters, High Speed, VLSI.- An Efficient Low Power and High Speed Distributed Arithmetic Design for FIR Filter
Authors
1 Department of Electronics and Communication Engineering, SRM University, Kanttankulathur - 603203, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai Campus, Chennai - 600127, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 4 (2016), Pagination:Abstract
Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.Keywords
Distributed Arithmetic (DA), Electro Cardio Gram (ECG), Finite Impulse Response (FIR), Look Up Table (LUT)- Low Power 64 Point FFT Processor
Authors
1 Department of ECE, SRM University, Chennai - 603203, Tamil Nadu, IN
2 School of Electronics Engineering, VIT University, Chennai - 632014, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 9, No 4 (2016), Pagination:Abstract
Objectives: This paper proposes a design of Low power FFT (Fast Fourier Transform) processor used in OFDM (Orthogonal Frequency Division Multiplexing) application as there is demand for low power design of portable communication device. Methods: This FFT processor is based on SDF (Single Path Delay Feedback) pipelined Architecture. Digit slicing multiplier less architecture aids in realizing the complex Multiplication. To reduce power dynamic power dissipation, the proposed architecture applies clock gating buffer. Control circuit is implemented using Gray code sequence instead of binary code sequence. The design proposed here is implemented in Verilog HDL. Cadence tool is used for synthesizing the proposed design Findings: The number of complex multiplication is also reduced by using radix -25 algorithms. The result shows reduced power consumption up to 25%. Improvements: This paper is presented for 64 Point FFT design; this can also be extended for Higher N point FFT design.Keywords
Clock Gating, FFT, Multiplier Less Multiplier, Radix 25, SDF- FPGA Implementation of Hiding Information using Cryptography
Authors
1 School of Electronics and Communication Engineering, VIT University, Chennai – 600127, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 8, No 19 (2015), Pagination:Abstract
Background: The main threat in communication is the unauthorized access of information third party without the knowledge of sender and receiver. Hence the security plays a vital role in data transmission systems. Confidential data like internet banking account passwords and email account passwords needs security in their text data. Data can be text, image, video and audio. Methods: The purpose of this research work is to implement a mechanism to hide information (image) using cryptography. Advanced Encryption Standard (AES) is a type of symmetric cryptography standard which can be used to transfer a block of information securely during transmission. Findings: The idea of this paper is to generate an encrypted image by giving image input to AES encryption system and getting the decrypted image as original image by giving encrypted image as input to the AES decryption system. The input image is given through MATLAB R2012b to ModelSim6.3 and the system simulation and synthesis is done by integrating Model Sim to the Altera DE2 115 board through Quartus II software. Conclusion: The maximum frequency attained from this workis 165.462MHz. Finally image is displayed through an LCD which is connected to the board using Video Graphics Array (VGA) Connector.Keywords
AES, Cryptography, Decryption, Encryption, Hiding- Performance Analysis of Real Time Operating System with General Purpose Operating System for Mobile Robotic System
Authors
1 School of Electronics Engineering, VIT University, Chennai – 600127, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 8, No 19 (2015), Pagination:Abstract
Background/Objectives: The objective of the paper is to analyze the General Purpose Operation System (GPOS) performance with Real Time Operating System(RTOS) using a mobile robot as a real time application. The mobile robot module is implemented on a single board computer having ARM11 as its core. Methods/Statistical Analysis: The method used to calculate response is realfeel method which uses dedicated timer and interrupt to calculate the response. Findings: The response of the mobile robot is calculated by interrupting the mobile robot with some obstacles. Findings:In addition to this, other parameters such as speed, rotations time and precision resulted by the sensor are also calculated. RTOS have an average of 20μs where as GPOS have an average of 102μs of response time in real time environment.Conclusion:The results show that RTOS has better response time than GPOS. The minimum distance required to stop the mobile robot in RTOS is more accurate than GPOS. Compare to GPOS, the RTOS is able to avoid the obstacle collision even for a shorter distance.Keywords
GPOS, Latency Calculation, Mobile Robot, Response Time, RTOS, Single Board Computer- Design of Fused Add-Multiply Operator using Modified Booth Recoder for Fast Arithmetic Circuits
Authors
1 School of Electronics Engineering, VIT University, Chennai - 600127, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 8, No 19 (2015), Pagination:Abstract
Background: In Digital Signal Processing (DSP) the complex arithmetic instructions are mostly used. The decoding of these instructions usually takes more time in many applications. Methods: The objective of this research work mainly focused on the delay reduction by decreasing the partial products with the help of higher radix booth recoder. The booth recoder plays a key role in fused add-multiply operation for partial product generation. Findings: The proposed fused add multiply unit reduces the delay by reducing the number of partial products which is very useful for fast arithmetic circuits. The fused add-multiply units are simulated in Xilinx® 14.3 ISE in Virtex-5 environment and synthesized in Cadence® RTL Compiler and layout generated from Cadence® Encounter in 180nm technology. Conclusion: Based on experimental results, it is observed that the delay of the proposed method is reduced by 17.5% than the existing work.Keywords
Accumulate Units, Booth Recorder, Fast Arithmetic, Fused Add Multiply, Multiply- Design of Signal Delay-Detection System by using Dual-Edge Trigger Flip Flops
Authors
1 School of Electronics Engineering, VIT University, Chennai - 600127, Tamil Nadu, IN
Source
Indian Journal of Science and Technology, Vol 8, No 20 (2015), Pagination:Abstract
Background: The conventional edge triggered flip-flops usually sample a data signal which is synchronizing with single clock edge. If any noise signal presents around the clock edge, then flip-flops result in malfunction. Methods: This research work presents the design mechanism of Signal Delay Detection System using Dual Edge Trigger Flip Flop (DETFF) which detects the delay occurs in the system and rectifies it to avoid the data loss. Dual Edge Trigger (DET) mechanism maintains the same throughput along with half of clock frequency when compared to the Single Edge Trigger (SET) mechanism. In conventional SET flip flops the sampling of data is done in synchronous with either rising or falling edge of clock since noise can occur across the clock edge which may results in malfunction of data signal. Findings: This problem is resolved by using DETFF as it samples the data at both rising and falling edges respectively with synchronous to clock signal. The DETFF is known for optimizing the noise in the systems by preventing the noise signal generated from different sources which in turn reduces the delay in the system. A new DETFF is proposed in order to improve the sampling capacity of the flip flop so that better optimization of delays can be achieved. Conclusion: This Proposed DET flip flop results in 42% of increment in size but improves the driving capability of flip flop, the operating speed is improved by 27% and 5% of reduction in power consumption.Keywords
Delay Detection Mechanism, Dual Edge Trigger, Flip Flop, Signal Delay.- Lymphangioma of Tongue - A Case Report
Authors
1 Professor, Department of Oral and Maxillofacial Surgery, Sree Balaji Dental College and Hospital, BIHER, Chennai, Tamilnadu, IN
Source
Indian Journal of Public Health Research & Development, Vol 10, No 11 (2019), Pagination: 3248-3249Abstract
Lymphangioma is a hamartomous benign tumour that is characterized by the proliferation of lymphatic vessels due to the congenital malformation of the lymphatic system. This benign tumour can occur anywhere in the body but head and neck being the common site of occurrence. However intraoral lymphangiomas are rare, if occurs it is more common on the dorsal surface of the tongue and the lateral border,and rarely occur in palatal mucosa, buccal mucosa, gingiva and lips. Lymphangiomas of tongue can be associated with difficulty in speech, mastication, chewing and maxillofacial deformities.
Surgical treatment is aimed at providing symptomatic relief; surgical excision remains the treatment of choice. However other treatment modalities like cryosurgery, electrocautery, sclerotherapy, radiation therapy, laser and tissue ablation can also be used3. We hereby present a case of 41 year old male with lymphangioma on the ventrum of the lateral surface of the tongue treated with surgical excision.
Keywords
Lymphangioma, Cryosurgery, Tongue.- Nasal Floor Reconstruction in Cleft Patient
Authors
1 Sree Balaji Dental College and Hospital, BIHER, Chennai, IN
Source
Indian Journal of Public Health Research & Development, Vol 10, No 11 (2019), Pagination: 3250-3253Abstract
Introduction: Widening of alar base width is often required in the lip/palate rehabilitation.the aims of this study is to evaluate such a procedure.
Materials and Method: This is a retrospective study. All cleft case requiring alar base widening were analysed, and the outcome presented at end of 4th and 8th month. This study was typical superomedially placed nasolabial full thickness flap to correct the alar base width simultaneously replaced the nasal lining.
Result: A total of three cleft patient underwent the procedure. Qualitative observation of the outcomes and postoperative changes with the resultant nasal alar base width are presented.
Discussion: The efficacy of this type of nasolabial flap for the alar basal widening and of nasal lining reconstruction is presented. The essential, functional and anatomical consideration in such a flap design is presented in this study.